The need often arises to generate phase shifted versions of a clock signal. Timing recovery circuits and delay-locked loops are two examples. Existing clock phase shifting circuits are based on cascaded delay cells, variable delay cells or mixing circuits. In the latter case, the output of the phase shift control is an analog signal which is prone to corruption by noise or crosstalk. Digital control can be achieved in this case through use of a digital-to-analog converter.
In some cases when CMOS and CML/ECL technologies are used in the same device, translators or resistive networks are needed to translate the CMOS control signal to an CML/ECL format. Provision of such circuits results in higher complexity and power dissipation.
In addition, mixed based clock phase shifter circuits typically have the phase control range limited to 90.degree..
CMOS and CML/ECL technologies are currently used within the same integrated circuit in an effort to reduce power dissipation and improve performance. Therefore, the need arises for a CMOS signal to act as the control signal for CML/ECL circuits, especially for high speed logic circuits.